1. Field of the Invention
The present invention relates generally to dielectric layers employed within microelectronics fabrications. More particularly, the present invention relates to methods for fabricating dielectric layers with improved properties within microelectronics fabrications.
2. Description of the Related Art
Integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to a semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit integration levels heave increased and integrated circuit device and patterned conductor element dimensions have decreased, various novel effects have evolved within integrated circuit devices which are fabricated within integrated circuit microelectronics fabrications. Within integrated circuit microelectronics fabrications within which are fabricated field effect transistors (FETs), a general group of detrimental effects arising incident to decreased field effect transistor (FET) dimensions within advanced integrated circuit microelectronics fabrications is known as short channel effects (SCEs). Within the general group of effects known as short channel effects (SCEs), a particularly common effect is the hot carrier effect (HCE). The hot carrier effect (HCE) derives from increased electrical fields within semiconductor substrates adjoining gate electrode edges within advanced field effect transistors (FETs) having comparatively thin gate dielectric layers of thickness from about 30 to about 60 angstroms, while operating at comparatively common operating voltages of from about 1.5 to about 3.5 volts. The increased electrical fields lead to increased charge carrier injection into the gate dielectric layers of the field effect transistors (FETs), which in turn leads to degradation of field effect transistor (FET) operating parameters such as but not limited to threshold voltage and drive current.
Beyond the hot carrier effect (HCE) which derives from both decreased gate dielectric layer thickness within a field effect transistor (FET) and decreased channel width within the field effect transistor (FET), there also exists within advanced field effect transistors (FETs) inherently decreased dopant diffusion barrier properties of comparatively thin gate dielectric layers with respect to dopants which are employed when doping polysilicon or polycide gate electrode layers within advanced field effect transistor (FETs). Such decreased dopant diffusion barrier properties are typically manifested with respect to mobile dopants, such as boron containing dopants, and they contribute to undesired doping of field effect transistor (FET) channel regions. Undesired doping of field effect transistor (FET) channel regions also compromises operating parameters of field effect transistors (FETs) within advanced integrated circuit microelectronics fabrications.
It is thus desirable in the art of integrated circuit microelectronics fabrication to provide methods and materials through which field effect transistors (FETs) may be fabricated with attenuated susceptibility to hot carrier effects (HCEs) and with enhanced dopant diffusion barrier properties of their gate dielectric layers.
It is towards those goals that the present invention is more specifically directed.
In a more general sense, the present invention is also directed towards forming within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications dielectric layers with enhanced properties, such as but not limited to dopant diffusion barrier properties.
Various methods have been disclosed in the art of integrated circuit microelectronics fabrication for fabricating dielectric layers with desirable properties within integrated circuit microelectronics fabrications.
For example, Young, in U.S. Pat. No. 4,214,919, discloses a method for forming for use within an integrated circuit microelectronics fabrication a thin silicon oxide dielectric layer free of a nitrogen pre-thermal oxidation environment induced micro-defects, such as shorts, which comprise performance of the integrated circuit microelectronics fabrication within which is formed the thin silicon oxide dielectric layer. The method employs in place of the nitrogen pre-thermal oxidation environment a pre-thermal oxidation environment employing at least in part argon when forming the thin silicon oxide dielectric layer.
In addition, Okada et al., in U.S. Pat. No. 5,407,870, discloses a method for forming a high reliability dielectric layer which may be employed within an integrated circuit microelectronics device such as but not limited to a field effect transistor (FET) or a capacitor. The high reliability dielectric layer employs a composite of a pair of silicon oxynitride dielectric layers separated by a silicon oxide dielectric layer.
Further Thakur et al., in U.S. Pat. No. 5,445,999, discloses a method for forming a uniform silicon nitride layer upon a monocrystalline silicon substrate layer or a polycrystalline silicon substrate layer within an integrated circuit microelectronics fabrication. The method employs a treatment of the monocrystalline silicon substrate layer or the polycrystalline silicon substrate layer with a reactive gas composition comprising at least one of argon-hydrogen, hydrogen, germane and nitrogen trifluoride diluted with argon-hydrogen, at a temperature of from about 850 to about 1150 degrees centigrade, to form a uniform dangling bond configuration upon the monocrystalline silicon substrate layer or polycrystalline silicon substrate layer prior to forming thereupon a silicon nitride layer through a rapid thermal nitridation method.
Yet further, Tseng et al., in U.S. Pat. No. 5,464,792, which is related to and co-assigned with U.S. Pat. No. 5,407,870, discloses a method for incorporating nitrogen at an interface of a dielectric layer opposite the interface of the dielectric layer with a semiconductor substrate employed within an integrated circuit microelectronics fabrication. The method employs a silicon buffer layer, such as amorphous silicon buffer layer or a polycrystalline silicon buffer layer, formed upon the dielectric layer, where upon forming upon the buffer layer an oxynitride layer and annealing the resulting integrated circuit microelectronics fabrication, nitrogen migrates to at least the interface of the buffer layer with the dielectric layer and possibly also to the interface of the dielectric layer with the silicon substrate.
Still yet further, Soleimani et al., in U.S. Pat. No. 5,596,218, discloses a method for forming a hot carrier resistant gate dielectric layer employed within a field effect transistor (FET) formed upon a semiconductor substrate within an integrated circuit microelectronics fabrication. The method employs implanting nitrogen ions into the semiconductor substrate and subsequently thermally oxidizing the semiconductor substrate to provide a gate dielectric layer having a peak nitrogen concentration near the gate dielectric layer interface with the semiconductor substrate.
Finally, Liu et al., in xe2x80x9cPreventing Boron Penetration Through 25-A Gate Oxides with Nitrogen Implant in the Si Substrate,xe2x80x9d IEEE Electron Device Lett., Vol. 16 (No. 5), May 1997, pp 212-14, similarly with Soleimani, in U.S. Pat. No. 5,596,218, also discloses an ion implant method for forming a hot carrier resistant and mobile dopant diffusion resistant gate dielectric layer for use within a field effect transistor (FET) within an integrated circuit microelectronics fabrication. Somewhat in contrast with the Soleimani, the gate dielectric layer so formed has a peak nitrogen content within the gate dielectric layer rather than at the interface of the gate dielectric layer with the silicon substrate.
Desirable in the art of microelectronics fabrication are additional methods and materials through which there may be formed within microelectronics fabrications dielectric layers with enhanced properties. More particularly desirable within the art of integrated circuit microelectronics fabrications are methods and materials through which gate dielectric layers employed within field effect transistors (FETs) within integrated circuit microelectronics fabrications may be fabricated with enhanced properties such as but not limited to enhanced hot carrier resistance properties and enhanced mobile dopant diffusion resistance properties.
It is towards the foregoing goals that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronics fabrication a dielectric layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the dielectric layer is a gate dielectric layer employed within a field effect transistor (FET) within an integrated circuit microelectronics fabrication.
A third object of the present invention is to provide a method in accord with the second object of the present invention, where the gate dielectric layer is formed with enhanced hot carrier resistance properties and enhanced mobile dopant diffusion barrier properties.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a dielectric layer upon a silicon layer. To practice the method of the present invention, there is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon layer. There is then formed through use of a first thermal annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material a silicon nitride containing layer upon a partially consumed silicon layer derived from the silicon layer. There is then oxidized through use of a second thermal annealing method employing an oxidizing material containing annealing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer formed upon a further consumed silicon layer derived from the partially consumed silicon layer.
The present invention provides a method for forming within a microelectronics fabrication a dielectric layer. The present invention realizes the foregoing object by forming through partial consumption of a silicon layer through a first annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material and a reducing material a silicon nitride containing layer and then oxidizing through further consumption of the partially consumed silicon layer through a second thermal annealing method employing an oxidizing material containing annealing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer which forms a dielectric layer.
The method of the present invention may be employed where the dielectric layer is a gate dielectric layer within a field effect transistor (FET) within an integrated circuit microelectronics fabrication. The present invention does not discriminate with respect to the nature of a dielectric layer which is formed employing the method of the present invention, provided that the dielectric layer is formed upon a silicon substrate layer within a microelectronics fabrication. Thus, the present invention may be employed where the dielectric layer is a gate dielectric layer which may be employed within a field effect transistor (FET) within an integrated circuit microelectronics fabrication, as well as other dielectric layers formed upon other silicon layers within other integrated circuit devices such as but not limited to capacitor dielectric layers within silicon layer capacitors, within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
When employed for forming a gate dielectric layer within a field effect transistor (FET) within an integrated circuit microelectronics fabrication, a gate dielectric layer formed in accord with the method of the present invention is formed with enhanced hot carrier resistance properties and enhanced mobile dopant diffusion barrier properties. In addition, when employed for forming dielectric layer including but not limited to gate dielectric layers within field effect transistors (FETs), the method of the present invention also generally provides dielectric layers with attenuated oxidation rates and enhanced dielectric layer uniformity.
The method of the present invention is readily commercially implemented. The method of the present invention provides that a silicon layer within an integrated circuit microelectronics fabrication is thermally annealed employing a first thermal annealing method within a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material to form a silicon nitride containing layer which is subsequently oxidized employing a second thermal annealing method employing an oxidizing material containing annealing atmosphere to form an oxidized silicon nitride containing layer. Since thermal annealing methods are generally known in the art of microelectronics fabrication, as are various materials which may be employed within those thermal annealing methods, the method of the present invention is readily commercially implemented.